1. Field of the Invention
The present invention relates to a liquid crystal display and pulse generation circuit for displaying images on the basis of input video signals, and more particularly to a liquid crystal display and pulse generation circuit in which the number of switching times for pulse strings is improved.
2. Background of the Invention
In general, when an image is displayed on a liquid crystal display (LCD), image signals are output from a graphics controller in a system unit or system part of a PC or the like via a video interface. An LCD controller LSI, which receives these image signals, supplies signals to each IC in a source driver (i.e., X driver, LCD driver) and gate driver (i.e., Y driver), and then a voltage is applied to each source electrode and each gate electrode in a TFT array arranged in a matrix fashion, thereby leading to displaying images.
As a configuration employed in this LCD source driver, technologies called chip-on-glass (COG) and wiring-on-array (WOA) have recently become the focus of attention. Also, a technology is being developed where a driver LSI is arranged in a TCP (tape carrier package) and connected to the TFT array substrate (glass substrate) via the TCP. It is expected that manufactures' costs will be reduced by applying these technologies to attach ICs directly on the glass substrate or via the TCP as well as to eliminate wiring on a printed circuit board.
On the other hand, there are mainly two types of digital-analog conversion circuits (DAC): one is a current summing scheme such as an R-2R ladder network type DAC in which there are provided as many current sources as the number of bits of digital input data, wherein the current is added depending on a value of each bit of the input data in order to obtain an output current corresponding to the input data; the other is a time control scheme such as an integral type DAC in which an output voltage is obtained by charging a capacitor for a time depending on the digital input data with a constant current. Furthermore, the time control scheme includes a pulse width modulation (PWM) type DAC in which an output voltage is obtained by integrating a pulse string whose duty is adjusted depending on the digital input data, and a pulse density modulation (PDM) type DAC in which an output voltage is obtained by integrating a pulse string wherein the number of pulses occurring within a predetermined time is adjusted depending on the digital input data.
In order to implement a reference voltage generation circuit for gamma correction that is built in the LCD source driver, in order to reduce the deviation of the reference voltage between drivers, these PWM or PDM type DACs are used. These DACs have a high applicability to LCDs since they are of the above-mentioned time control scheme, wherein a difference of the output voltage is unlikely to be introduced due to dispersion of resistors and capacitors created in the chip.
FIG. 13 depicts a configuration of a typical PDM type DAC. The PDM type DAC comprises a pulse generation circuit 201 for generating a plurality of reference pulses in which pulse generation densities are weighted, a digital input data latch 202 for storing digital input data, a pulse select/synthesis circuit 203 for generating a pulse string by selecting and synthesizing necessary reference pulses on the basis of generated reference pulses and input data, a voltage conversion circuit 204 for converting a pulse string generated by a digital power supply into a desired analog voltage range, and an integration circuit (low pass filter) 205 for converting a pulse string into an analog voltage.
For a PDM type DAC as shown in FIG. 13, since a frequency of the pulse string is able to be increased compared with a PWM type DAC, resistors and capacitors used in integration circuit 205 are reduced, which preferably makes a chip area small, thereby saving costs. On the contrary, power consumption is increased due to the increase of frequency of the pulse string, and moreover the linearity of the output voltage is deteriorated because the number of switching times differs for pulse strings corresponding to each of digital input data.
FIG. 14 depicts a schematic diagram of pulse generation circuit 201 for use in a PDM type DAC for liquid crystal displays. The circuit shown in FIG. 14 is used in the case of 9 bit DAC, which comprises a 9 bit binary counter 210, a 9 bit latch 211, and nine 2-input AND gates 212. By ANDing counter outputs from binary counter 210 with negative latched outputs from 9 bit latch 211, weighted pulses are generated at the reference pulse outputs X8 through X0. Assuming the pulse density of X0 is 1, those of X1, X2, X3, X4, X5, X6, X7 and X8 are 2, 4, 8, 16, 32, 64, 128, 256, respectively. It is also noted that since the reference pulses X0 through X8 are generated such that they become high exclusively, these pulses never overlap temporally each other even if any plural number of reference pulses are synthesized.
FIG. 15 depicts a waveform of pulse outputs (X8 through X5) of a PDM type DAC. Also shown in FIG. 15 are the outputs (B0 through B3) of binary counter 210 and outputs (L0 through L3) of 9-bit latch 211. For example, ANDing a counter output B1 with an inverted latch output L1 produces a pulse output X7 at the rising edge of a counter output B1. In this manner, pulse outputs (X8 through X0) are obtained. In the PDM type DAC, pulse select/synthesis circuit 203 selects pulse outputs X8 through X0 depending on the value of each of the bits of digital input data and then ORs them for the purpose of synthesis to generate a pulse string corresponding to the digital input data. For example, when digital input data is 320 (B101000000), reference pulses X8 and X6 are selected because their corresponding bits in the input data are 1, and then a pulse string is generated by synthesizing X8 and X6, and then sent to voltage conversion circuit 204 where its voltage is converted, and finally being input to integration circuit 205.
FIG. 16 is a diagram illustrating a relationship between each digital input data and its corresponding frequency of the pulse string for a PDM type DAC for liquid crystal displays. It is noted that the operating frequency (i.e., clock input) of a counter and latch is 120 MHz. As is seen from FIG. 16, as digital input data increases from 0 to 256, the frequency of the pulse string also increases monotonously, wherein it reaches a maximum frequency of 60 MHz when the input data is 256, while as digital input data increases from 256 to 511, the frequency of the pulse string decreases monotonously. In this manner, since the frequency of the pulse string varies depending on digital input data (i.e., the number of switching times of a circuit for driving integration circuit 205 behind also varies), a degree of influence of switching upon the analog output voltage varies for each digital input data. This deteriorates the linearity of analog output voltage for DACs. Moreover, if the values of resistors and capacitors used for integration circuit 205 are set to match with pulse strings with low frequencies (i.e., around 0 or 511 of digital input data), the frequency of pulse strings becomes too high around a medium value (256) of the digital input data, resulting in unwanted power consumption.